IEC 62148-21 pdf – Fibre optic active components and devices – Package and interface standards – Part 21: Design guidelines of electrical interface of PIC packages using silicon fine-pitch ball grid array (S-FBGA) and silicon fine-pitch land grid array (S‑FLGA)

IEC 62148-21 pdf – Fibre optic active components and devices – Package and interface standards – Part 21: Design guidelines of electrical interface of PIC packages using silicon fine-pitch ball grid array (S-FBGA) and silicon fine-pitch land grid array (S‑FLGA)
This part of IEC 62148 covers the design guidelines of the electrical interface for photonicintegrated circuit (PIlC) packages using silicon fine-pitch ball grid array(S-FBGA) and siliconfine-pitch land grid array (S-FLGA). In this document,the electrical interface for the S-FBGApackage is informative.
The purpose of this document is to specify adequately the electrical interface of PIC packages
composed of optical transmitters and receivers that enable mechanical and electricalinterchangeability of PIC packages.
Normative references
The following documents are referred to in the text in such a way that some or all of their contentconstitutes requirements of this document. For dated references, only the edition cited applies.
For undated references， the latest edition of the referenced document(including anyamendments) applies.
IEC 60050-731,International Electrotechnical Vocabulary – Chapter 731: Optical fibrecommunication (available at www.electropedia.org)
IEC TR 61931,Fibre optic – Terminology
3 Terms and definitions
For the purposes of this document,the terms and definitions given in IEC 60050-731,IEC TR 61931 and the following apply.
IsO and lEC maintain terminological databases for use in standardization at the followingaddresses:
.lEC Electropedia: available at http://www.electropedia.orgl
.Iso online browsing platform: available at http://www.iso.orglobp
3.1
silicon fine-pitch ball grid arrayS-FBGA
device composed of silicon die, dielectric layer(s) on the die, rerouting wires from the die padsto outer balls on the dielectric layer(s), and outer balls with heights more than 0,1 mm
3.2
silicon fine-pitch land grid arrayS-FLGA
device composed of silicon die, dielectric layer(s) on the die, rerouting wires from the die padsto outer lands on the dielectric layer(s), and outer lands with heights of 0,1 mm or less
4 Terminal position numbering When a package is viewed from the terminal side with the index corner in the bottom left corner position, terminal rows are lettered from bottom to top starting with A, then B, C…, AA, AB, etc.; whereas terminal columns are numbered from left to right starting with 1. Terminal positions are designated by a row-column grid system and shown as alphanumeric identification, for example A1, B1. The letters I, O, Q, S, X and Z shall not be used for naming the terminal rows.
5 Code of package nominal dimensions A code of package nominal dimensions is defined as the combination of package length E and width D, which are shown to the second decimal place in millimetres.
6 Symbols and drawings Figure 1 shows the dimensions of the package and the outline of the electrical interface for S- FBGA and S-FLGA. Figure 1 also shows the dimensions of the optical terminal area and its guard band area. The electrical terminal is freely allocated to the terminal positions defined by the cross points of the row-column grid numbers, as long as its position is outside of the optical terminal guard band area. The optical interface shall be designed within the optical terminal area. Figure 2 and Figure 3 indicate the mechanical gauge drawing and its array of electrical terminal existence area. Figure 2 shows the electrical terminal existing area referred to data S, A and B. Figure 3 shows the electrical terminal existing area referred to datum S .